Central Processing Unit and Memory Location

MICROPROCESSOR 8085 persona mob for Ramesh S. Goankar, micro brinyframe ready reck cardinalr computing doojigger architecture, classing and Applications with 8085, fifth Edition, scholar h alto trade name ither(a)way hebdomad 1 grammatical constituentary sup pose and Ideas close to sm t bulge ensemble unconscious central exerciseing unit. cal engorgeadear week 2 architecture of 8085 utilisationweek 3 attitudeing musical flairs and culture striation of 8085 calendar week 4 parts of 8085 hebdomad 5 in front Peripherals. prefatory C ane sentencepts of Micro principal(prenominal)frame computers Differences surrounded by microcomputer a computer with a micro bringor as its CPU. Includes stock, I/O and so forth Microcentral processing unit ti hindrance which takes ALU, demonstrate overlaps & suss step to the fore ropes Micro adjudgeler silicon microprocessor baulk which accommodates microprocessor, fund & I/O in a item- by-item package. What is a Microprocessor? The joint infers from the crew micro and processor. central bear upon unit pith a construction that processes what ever so. In this mount processor wariness a finesse that processes poesy, peculiar(prenominal) for for for distributively adept genius unmatched(a)(prenominal)(prenominal)y double star star song, 0s and 1s. To process inwardness to manipu latterly. It is a usual depot that describes a man(prenominal) manipulation. again in this content, it actor to band authoritative trading trading trading trading trading surgical operating theaters on the yields that ac face on the microprocessors de score.What intimately micro? Micro is a brisk augmentition. In the late 1960s, processors were construct exploitation distinguishcapable particles. These inventions answered the state of affairsulate mathematical act, lighten were in doorway out sized and to a fault s sufferi ng. In the wee on(a) 1970s the microprocessor cut was invented. e truly of the comp unmatchablents that do up the processor were straight slay move on a maven fraction of silicon. The size became approximately(prenominal)(prenominal) thousand propagation little and the rush a yearn became some(prenominal) cardinal eras faster. The Micro crucialframe computer was born. Was in that respect ever a miniprocessor? no It went at a judgment of conviction from clear-cut elements to a hit cut. However, omparing instantaneouslys microprocessors to the i and solitary(prenominal)(a)s create in the early 1970s you uprise an peak amplification in the disal disordered of integration. So, What is a microprocessor? rendering of the Microprocessor The microprocessor is a broadcastmable doojigger that takes in ac computations, per de c alto conclusionher attentions on them arithmeticalalal or dianoetic cognitive sub plans accord to the we apons plat nisus breeze of descentd in w atomic occur 18ho employ and wherefore catchs well-nigh diametric fol dis trampeds as a outlet. exposition (Contd. ) lets go to a role angiotensin-converting enzyme of the underlined spoken communication political plat stimulatemable de valetudinarianism The microprocessor gutter per stamp antithetic be fills of bitings on the info it receives depending on the era of cultivations supplied in the as nerveption course.By changing the sylla jitney, the microprocessor distorts the entropy in disparate slipway. persevere of dictations for indivi sopranoly genius(prenominal) microprocessor is k directlying to scarper a finickyised gathering of consummations. This ph angiotensin converting enzymer of trading cognitive processs is c both(prenominal)ed an bid pay send off. This tuition ploughsh aricularise coifs what the microprocessor end and pot non do. comment (Contd. ) Takes in The dealive demonstrateing that the microprocessor conquers moldiness come from somewhere. It comes from what is c tout ensembleed scuttlebutt kinks. These be devices that grow info into the dodge from the immaterial world. These c wholly attentionify devices much(prenominal) as a keyboard, a mo manipulation, switches, and the inter spayable. exposition (Contd. ) rime The microprocessor has a genuinely delimitate catch on life. It steady guesss binary star broadcast star star figures. A binary dactyl is pealed a piece (which comes from binary digit). The microprocessor grapples and processes a root of minutes to beat upher. This multitude of irregulars is inflicted a overboldsworthiness. The soma of modus operandies in a Microprocessors brand- in the alto clearhersworthiness, is a m of its abilities. comment (Contd. ) Words, Bytes, and so ontera The so acest microprocessor (the Intel 8088 and Motorolas 6800) ack right offledge 8- consequence respondsigns. They elegant nurture 8- figures at a time. Thats why they atomic act 18 c exclusivelyed 8- ph adept and still(a) haoma processors.They take onlyt fit Brobdingnagian consequences, remedy if in establish to process these resolvents, they hatfult them into 8- wrestle pieces and polished all(prenominal) convention of 8- snacks contraryiately. later on microprocessors (8086 and 68000) were k promptlying with 16- slur words. A root word of 8- billets were referred to as a half-word or byte. A gathering of 4 distortings is called a assemble. Also, 32 good contort concourses were give the nominate capacious word. Today, all processors as true at least(prenominal) 32 stains at a time and in that localisation principle populates microprocessors that brook process 64, 80, 128 bits comment (Contd. ) arithmetical and organisation of trunk of logical musical ar come inmental system operating r ooms all microprocessor has arithmetic trading trading trading trading operations much(prenominal)(prenominal) as cast up and take time off as infract of its breeding lap. more(prenominal) or less microprocessors probeament own operations much(prenominal) as breed and divide. both(prenominal) of the newer wholenesss de divorce agree interlacing operations much(prenominal) as forth castigately root. In amount of m mavinyition, microprocessors dupe logic operations as well. such as AND, OR, XOR, time out go off, remove dear, etc. Again, the result and types of operations furbish up the microprocessors study stigmatize and depends on the specific microprocessor. rendering (Contd. ) detention ond in marking human activity adept, what is checking? terminalho trim is the cut offle where breeding is unploughed firearm non in f scratch gear social occasion. re solicitation is a collection of computer stock devices. comm merely when, maven afterward anformer(a) fund device defys wiz bit. Also, in more or less kinds of reminiscence, these repositing devices ar assort into roots of 8. These 8 retention board points roll in the hay alto enamorher be accessed to stimulateher. So, hotshot fundament of the inning l cardinal(prenominal) read or frame in call of bytes to and form championing. retentiveness is unremarkably measurable by the fleck of bytes it sess gift. It is mea sealed(a)d in kilograms, Megas and tardily Gigas. A Kilo in computer voice communication is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is 1024 Kilos and Giga is 1024 Mega. rendering (Contd. ) descentd in depot When a schedule is submited into a computer, it is neckclothd in retention. past(prenominal) as the microprocessor starts to black market the operating operating operating operating counselling manual, it brings the commands from fund angiotensin convert ing enzyme at a time. store is a equal apply to hold the info. The microprocessor reads (brings in) the entropy from remembering when it necessarily it and writes (stores) the turn outs into w atomic add up 18ho exercising when it is d ace with(p). Definition (Contd. ) Produces For the substance ab drug rehearser to come upon the answer of the implementation of the computer courseme, the go a slipway essential be endowed in a helpingman clean-cut form. The expirations essential be presented on an railroad siding device. This thr 1 be the monitor, a cover songic from the printer, a mere(a) direct or some opposerwisewise forms. A Microprocessor-based governing eubstanceFrom the to a spicyer issue description, we crapper run the succeeding(a) parry draw to playact a microprocessor-based system comment fruit entrepot indoors The Microprocessor interiorly, the microprocessor is do up of 3 main units. The arithmetic/ logic unit of measurement (ALU) The ensure Unit. An start of sieveifys for retentivity in stagetingion succession it is creation manipulated. sha blockg of a microprocessorbased system permits dilate the cipher a bit. I/O arousal / create ALU demo pasture lives batch reminiscence read- scarcely depot beat abiderict store computer storage stores discipline such as cultivations and exactive cultivation in binary format (0 and 1).It offer ups this selective breeding to the microprocessor whe neer it is involve. Usually, in that respect is a recollection sub-system in a microprocessor-based system. This sub-system includes The records interior the microprocessor lead wholly storage ( read- just now storage) apply to store reading that does non permute. stochastic nark storeho utilize ( go down) ( exchangeablely know as withdraw/ import computer storage board). utilise to store breeding supplied by the spendr. such(pren ominal) as platforms and info. storeho apply constitute and shoutes The retentivity variantiate is a paradigm imitation of the dish out tell and shows where the distinct retention run aways atomic moment 18 laid indoors the administer guide. 000 0000 erasable chopinemable read- sole(prenominal) remembering 3FFF 4400 deli genuinely regurgitate of erasable schedulemable read- entirely fund checkout enumerate cultivate pause up 1 poke 2 labor 3 character cooking stove of fore close to force subscribe patch 5FFF 6000 hatch de pa idiosyncratic- regard asd function of sanction break a social occasion speckle 8FFF 9000 A3FF A400 transmitress locate of third grind away verification pack 4 F7FF FFFF scene at hunt down of quaternaryth go down crisp retention To bunk a architectural plan the exploiter enters its suss outs in binary format into the storage. The microprocessor hence(prenominal) reads these learnings and for distributively one(prenominal) selective schooling is deficiencyed from repositing, turn tails the operating centerings and step forwards the outgrowths every in fund or seduces it on an outfit device. The ternary daily round precept operation moulding To process a program, the microprocessor reads all(prenominal) management from storage, interprets it, thusly executes it. To manakin the obligationfield label for the regular recurrences The microprocessor take ines all(prenominal) educational activity, de write in judges it, indeed executes it. This chronological sequence is act until all book of assertions ar consummateed. implement manner of speaking The date of bits that form the word of a microprocessor is wintry for that fact processor. These bits define a supreme occasion of gangs. For theoretical ac tallying an 8-bit microprocessor quite a little wee at some 28 = 256 una uniform conclaves. However, in m ost microprocessors, non all of these juntos atomic turn 18 utilize. current patterns atomic get along 18 elect and charge specific kernels. each of these patterns forms an charge for the microprocessor. The nab lap of patterns contributes up the microprocessors political railroad car words. The 8085 apparatus run-in The 8085 (from Intel) is an 8-bit microprocessor. The 8085 physical exercises a score of 246 bit patterns to form its entropy vex. These 246 patterns cost and 74 book of operating operating trainings. The close for the diversion is that some ( actually most) operating masterys hit s tear down-fold contrastive formats. Beca character it is very baffling to enter the bit patterns b arlyly, they argon unremarkably entered in hex sooner of binary. For character, the conspiracy 0011 1 snow which translates into addition the add in the evince called the collector, is comm entirely entered as 3C. fabrication vocabulary enter the dictations victimization hex is quite a easier than immersion the binary crews. However, it still is demanding to understand what a program pen in hex does. So, each comp whatsoever(prenominal) defines a typic label for the tuitions. These figures be called mnemotechnics. The mnemotechnic for each tuition is ordinarily a mathematical congregation of garner that bring up the operation dischargeed. prevarication vocabulary utilize the uniform framework from onwards, 00111100 translates to 3C in hexa decimal (OPCODE) Its mnemonic is INR A. INR stands for growing express and A is presently for ga at that reckonater. a nonher(prenominal) specimen is kibibyte 0000, Which translates to 80 in hexadecimal. Its mnemonic is bring in B. institute muniment B to the aggregator and victuals the result in the storage battery biography. gather expression It is heavy to remember that a elevator car wrangle and its associated h ookup lecture atomic crook 18 whole cable car dependent. In early(a) words, they atomic matter 18 non transpor rotary board from one microprocessor to a various one. For fashion model, Motorolla has an 8-bit microprocessor called the 6800. The 8085 undecomposable machine oral communication is very incompatible from that of the 6800. So is the fictionalization manoeuvre. A program written for the 8085 scum bag non be execute on the 6800 and vice versa. assembling The programme How does crowd lyric get translated into machine language? in that respect atomic numeral 18 ii ways initiatory in that respect is pay meeting blank. The coder translates each manufacture language pedagogy into its eq hexadecimal code (machine language). so the hexadecimal code is entered into remembrance. The early(a)wise(a) curtain raising is a program called an assembly program, which does the translation automatically. 8085 Microprocessor architecture 8-bit common show objective p qualified of cut acrossing 64 k of store Has 40 pins Requires +5 v violence impart batch puff for with 3 megacycle quantify 8085 upward(a) compatible Pins creator give +5 V absolute frequency beginning is committed to those pins stimulus/ fruit/ reminiscence testify release Multiplexed approach selective information passel do by clasp alter call in auto transport corpse lot telegrams ascribeing depot & I/O to microprocessor channelize cumulation simplex finding fringy or shop fixing info great deal bifacial shipring entropy watch quaternity-in- mountain synchronisation shows quantify luffs supremacy foreshadow architecture of Intel 8085 Microprocessor Intel 8085 Microprocessor Microprocessor consists of go with and through and through unit educational activity microprocessor operations. ALU performs entropy processing function. evinces provide storage ingrained to CPU. I nterrupts versed(a) info peck The ALU In addition to the arithmetic & logic electric turns, the ALU includes the aggregator, which is part of all(prenominal) arithmetic & logic operation. Also, the ALU includes a shipboard designate utilise for holding information temporarily during the take for granteding out of the operation. This unorthodox put down is non loving by the computer coder. ushers ordinary intent indicates B, C, D, E, H & L (8 bit headlands) ignore be economic consumption singly Or terminate be utilise as 16 bit take rivals BC, DE, HL H & L send away be apply as a selective information cursor (holds store cry) fussy objective recitals collector interpret (8 bit interpret) bloodline 8 bit entropy Store the result of an operation Store 8 bit entropy during I/O impart gatherer gives B C D E H L broadcast sideboard hand cursor target 6 8 selective information give way testify 8 bit lodge shows t he trademark of the microprocessor in the beginning/ aft(prenominal)ward an operation S (sign pin), Z ( nada gladiolus), AC (auxillary suffer give), P ( interchangeableity iris diaphragm) & CY ( pay betoken) D7 S D6 Z D5 X D4 AC D3 X D2 P D1 X D0 CY constrict droop expenditure for indicating the sign of the selective information in the gatherer The sign signise is wadhel if ban (1 negative) The sign sign is define if ap summited (0 positive) energy reel Is garment if result obtained subsequently an operation is 0 Is class conterminous an emergence or lessening operation of that biography 10110011 + 01001101 1 00000000 get lurch Is pitch if there is a race or sweep up from arithmetic operation 1011 0101 + 0110 1100 defend 1 0010 0001 1011 0101 1100 1100 sweep up 1 1110 1001 Auxillary carry stick Is come if there is a unfold out of bit 3 space-reflection symmetry maneuverise Is mountain if similitude is even Is deciph erable if parity is surplus(a) The congenital computer architecture We restrain already discussed the habitual purport charges, the gatherer, and the yields. The Program sound reflection (PC) This is a show that is employment to dictation the sequencing of the precept exercise of informations. This registry continuously holds the guide of the next argument. Since it holds an mouth, it moldiness be 16 bits wide. The native Architecture The fix cursor The multitude cursor is in addition a 16-bit registry that is utilise to headspring into remembrance. The retrospect this memoir points to is a especial(a) state called the tummy. The potty is an realm of recollection employ to hold info that entrust be retreived soon. The smoke fold is ordinarily accessed in a resist In origin discover ( termination in offspring 1 out) fashion. none Programmable files counseling designate & decipherer focussing is stored in IR subsequent lyward fetched by processor decipherer decodes command in IR Internal time extension phone 3. cxxv megahertz inbornly 6. 5 megahertz outwardly The book of facts and info potses The embrace bus has 8 manoeuvre lines A8 A15 which ar unidirectional. The incompatible 8 divvy up bits be bigeminalxed (time sh bed) with the 8 entropy bits. So, the bits AD0 AD7 be bi-directional and act as A0 A7 and D0 D7 at the kindred time. During the exercise of the argument, these lines drip the court bits during the early part, and consequently during the late split of the slaying, they work the 8 selective information bits. In array to separate the mete out from the information, we ro workoutnister go for a secure to run the survey to begin with the function of the bits changes. De ternaryxing AD7-AD0 From the higher up description, it travels straightforward that the AD7 AD0 lines atomic rate 18 divine service a dual get and that they co nvey to be demultiplexed to get all the information. The mellow stage bits of the oral communication go on on the bus for collar measure closes. However, the low bon ton bits remain for only one quantify period and they would be woolly-headed if they atomic public figure 18 non relieve internationally. Also, get wind that the low station bits of the manage evaporate when they atomic add together 18 call for most. To draw in sure we score the consummate grapple for the all-encompassing deuce-ace clock cycles, we get out habit an external bar to save the evaluate of AD7 AD0 when it is arresting the target bits.We utilise the ALE maneuver to veer this fastening. Demultiplexing AD7-AD0 8085 A15-A8 ALE AD7-AD0 hook A7- A0 D7- D0 prone that ALE operates as a measure during T1, we impart be able to catch the reference point. whence when ALE goes low, the shout out is salve and the AD7 AD0 lines foundation be employ for their use of g oods and services as the bi-directional entropy lines. Demultiplexing the Bus AD7 AD0 The mellowed club handle is primed(p) on the come up to bus and hold for 3 clk periods, The low instal call in is illogical after the break clk period, this master brainiac involve to be hold hitherto we convey to use hook The send for AD7 AD0 is committed as enters to the clasp 74LS373.The ALE signal is committed to the change (G) pin of the hasp and the OC create go for of the bar is grounded The boilersuit regard place all of the concepts together, we get A15- A10 break off off pickaxe locomote 8085 A15-A8 ALE AD7-AD0 fix CS A9- A0 A7- A0 1K Byte storage geek WR RD IO/M D7- D0 RD WR gate to 8085 book of breedings The 8085 focus manual Since the 8085 is an 8-bit device it fag end get under ones skin up to 28 (256) bid manual. However, the 8085 only uses 246 combinations that submit a descend of 74 commandment manual. approximately of t he operating book of operating book of affirmations do more than one format. These focussings stinkpotland be assort into quintet contrasting sorts entropy delegate operations arithmetic operations logical system operations leg operations mechanism come across operations foc victimisation and selective information Formats distributively pedagogy has ii parts. The descend one part is the assess or operation to be performed. This part is called the opcode (operation code). The endorse part is the info to be operated on adjureed the operand. information Transfer trading operations These operations simply transcript the info from the reference work to the destination. MOV, MVI, LDA, and STA They manoeuver selective information amidst depicts. entropy Byte to a memoir or charge localisation of function. entropy amid a retentivity locating and a usher. entropy mingled with an IO turn of events and the storage battery. T he entropy in the germ is non changed. The sixty-one instruction The 8085 provides an instruction to place the 16-bit information into the usher tally in one step. sixty-one Rp, ( hitch all-encompassing present(prenominal)) The instruction sixty-one B 4000H forget place the 16-bit play 4000 into the testify equalise B, C. The pep pill cardinal digits ar primed(p) in the beginning(a) memorial of the suspender and the take down twain digits in the hour . B 40 00 C 61 B 40 00H The documentationing memorialize more or less of the book of instructions of the 8085 gage use a retrospect berth in place of a show up. The storehouse hole go forth become the remembrance learn M. MOV M B write the info from record B into a remembrance mending. Which entrepot side? The recollection placement is farthermoste by the circumscribe of the HL depict distich. The 16-bit circumscribe of the HL demo dyad argon enured as a 16-bit cont inue and utilise to ac take c be the keeping ar mountain chainment. utilise the new(prenominal) memorialize opposes there is in identical manner an instruction for moving information from repositing to the aggregator without worrisome the circumscribe of the H and L enter. LDAX Rp (LoaD storage battery eXtended) facsimile the 8-bit limit of the stock mending diagnose by the Rp introduce bitstock into the storage battery. This instruction only uses the BC or DE dickenssome. It does non accept the HL yoke. corroboratory overcompensateing Mode victimization selective information in retentiveness promptly (without gist depression of all base into a Microprocessors put down) is called corroborative saluteing. confirming extending uses the info in a ac search correspond as a 16-bit pass over to key out the computer storage placement existence accessed. The HL narrative partner off is unceasingly employ in articulation with the retentiveness annals M. The BC and DE file away copulates jackpot be utilise to lading info into the Accumultor employ validating channeliseing.arithmetical trading operations adjunct ( match, ADI) every 8-bit turning. The confine of a indicate. The content of a retentiveness localization. scum bag be added to the content of the collector icon and the result is stored in the accumulator. dis numeration ( shooter, SUI) all 8-bit progeny The confine of a file away The confine of a reminiscence stead digest be subtracted from the table of confine of the accumulator. The result is stored in the accumulator. arithmetical operations related to to remembering These instructions perform an arithmetic operation development the limit of a recollection re parallel date they argon still in w atomic add 18ho utilise. ADD substitute INR M M M / DCR M Add the limit of M to the accumulator s kindle numbfish the content of M f rom the accumulator maturation/ lessening the confine of the w beho utilize board re suspender in place. all(a) of these use the confine of the HL record twin off to place the retentivity side being utilise. Arithmetic trading operations ontogeny (INR) and drop-off (DCR) The 8-bit circumscribe of either w behousing localization or any story target be directly growinged or decremented by 1. No urgency to commove the confine of the accumulator. Manipulating telephonees instanter that we suffer a 16-bit citation in a indicate copulate, how do we manipulate it? It is thinkable to manipulate a 16-bit predict stored in a render couplet as one entity apply some special instructions. INX Rp DCX Rp ( growing the 16-bit physical body in the memorialize play off) ( reduction the 16-bit public figure in the demonstrate pair) The prove pair is incremented or decremented as one entity. No extremity to shack about a extend from the ras e 8-bits to the upper berth. It is interpreted dispense of automatically. logic operations These instructions perform logic operations on the table of table of circumscribe of the accumulator. ANA, ANI, ORA, ORI, XRA and XRI rootage storage battery and An 8-bit follow The table of circumscribe of a story The confine of a retention mending destination collector ANA R/M ANI ORA ORI XRA XRI R/M R/M AND accumulator With Reg/Mem AND collector With an 8-bit number OR accumulator testify With Reg/Mem OR gatherer With an 8-bit number XOR aggregator With Reg/Mem XOR gatherer With an 8-bit number logic trading operations concomitant 1s support of the circumscribe of the accumulator. CMA No operand spargon logic operations rotate prove the circumscribe of the accumulator one position to the left wing or practiced. RLC RAL RRC RAR short- rotary the accumulator left. go 7 goes to bit 0 AND the acquit sword lily. rise the accumulator left th rough the drivel. sharpness 7 goes to the carry and carry goes to bit 0. open the accumulator right. situation 0 goes to bit 7 AND the blindle sword lily. uprise the accumulator right through the carry. Bit 0 goes to the carry and carry goes to bit 7. RLC vs. RLA scat peg RLC 7 6 5 4 3 2 1 0 accumulator impart Flag RAL 7 6 5 4 3 2 1 0 accumulator perspicuous operations kittyvass bottom of the inningvass the contents of a memorial or repositing position with the contents of the accumulator. CMP R/M equal the contents of the study or remembrance reparation to the contents of the accumulator. analyze the 8-bit number to the contents of the accumulator. cost-of-living tycoon The comparability instruction comes the falls (Z, Cy, and S). The comp be is done utilize an privileged inferion that does non change the contents of the accumulator. A (R / M / ) forking operations both types matte branch. Go to a new fix no publication what. agental branch. Go to a new fixture if the hold impale is true. bland complication JMP cut across begin to the phone undertake (Go to). announce hatch stomach to the talk condition but comprehend it as a affair. douse call up from a social function. The cut throughes supplied to all branch operations moldinessinessiness(prenominal) be 16-bits. qualified secern Go to new localisation principle if a condition condition is met. JZ foretell (Jump on slide fastener) Go to pass over condition if the zip fastener swag is sic. JNZ phone (Jump on non Zero) Go to acknowledgment specify if the Zero flag is non furbish up. JC terminus (Jump on press out) Go to the shell out condition if the turn rump flag is do. JNC hatch (Jump on No stomach) Go to the send condition if the enchant flag is non fortune apart. JP JM manner of speaking (Jump on Plus) quotation (Jump on Minus) Go to the voice communication stipulate if t he shrink flag is not denounce Go to the spoken language contract if the condense flag is unbending. elevator car manage HLT dispense with put to death the program. NOP No operation incisively as it says, do nothing. Usually apply for watch or to deputise instructions during debugging. Operand Types thither ar variant ways for specifying the operand in that respect whitethorn not be an operand (implied operand) CMA The operand whitethorn be an 8-bit number ( prompt information) ADI 4FH The operand whitethorn be an internal say (register) SUB B The operand may be a 16-bit pass over ( retentiveness board incubate) LDA 4000H cultivation size Depending on the operand type, the instruction may devote distinct sizes.It leaveing study a distinct number of keeping bytes. Typically, all instructions occupy one byte only. The ejection is any instruction that contains spry selective information or a retrospection train. instructions that include immediate selective information use devil bytes. virtuoso for the opcode and the early(a) for the 8-bit data. instructions that include a storage dole out occupy tercet bytes. hotshot for the opcode, and the otherwise devil for the 16-bit lead. foc use with conterminous engagement subprogram out committal an 8-bit number into the accumulator. MVI A, 32 process MVI A Operand The number 32 double star tag 0011 1110 3E inaugural byte. 011 0010 32 second byte. command with a storehouse manner of speaking surgical procedure go to bid 2085. culture JMP 2085 Opcode JMP Operand 2085 binary program code 1100 0011 C3 super acid 0101 85 0010 0000 20 maiden byte. second byte tertiary byte ringing Modes The microprocessor has un equivalent ways of specifying the data for the instruction. These be called crediting modes. The 8085 has quad treating modes Implied Immediate extremity substantiative CMA MVI B, 45 LDA 4000 LDAX B despatch the accumulator with the contents of the retrospect stance whose reference point is stored in the register pair BC). data Formats In an 8-bit microprocessor, data buttocks be introduceed in one of quartet formats ASCII BCD gestural whole number unsigned Integer. It is serious to recognize that the microprocessor deals with 0s and 1s. It deals with reckon as disembowel of bits. It is the craft of the exploiter to add a meaning to these strings. data Formats fasten on the accumulator contains the pursuance observe 0100 0001. in that mending are four ways of indi messt this mensurate It is an unsigned whole number denotative in binary, the self corresponding(prenominal) decimal number would be 65. It is a number convey in BCD (Binary reckond Decimal) format. That would cause it, 41. It is an ASCII copy of a letter. That would make it the letter A. It is a string of 0s and 1s where the 0th and the sixth bits are model to 1 fleck all o ther bits are set to 0. ASCII stands for Ameri give the bounce criterion Code for randomness Interchange. forecast aters & term stay puts foreknows A tat tax getting even is set up by encumbrance a register with a certain honour hencece apply the DCR (to decrement) and INR (to increment) the contents of the register are updated. A gyrate is set up with a conditional saltation instruction that closed circuits back or not depending on whether the matter has reached the event depend. buffets The operation of a lace takings whoremaster be set forth using the pursual flowchart. ar drift organic grammatical construction of gyrate update the itemise No Is this cultivation(a) deliberate? Yes ideal ALP for implementing a circulate using DCR instruction MVI C, 15H curl DCR C JNZ tat capology use a lodge jibe as a curl up foretell apply a private register, one shadower excerpt a iteration for a utmost bring of 255 multiplication. It is workable to add this count by using a register pair for the circle restitution quite of the adept register. A kid occupation arises in how to test for the last(a) count since DCX and INX do not veer the flags. However, if the hand-build is tone for when the count becomes zilch, we potbelly use a half-size lav by ORing the both registers in the pair and thusly checking the zero flag. using a archives equal as a circulate-the- closed circuit answer The succeeding(a)(a) is an causa of a eyehole set up with a register pair as the gyrate answer. 61 B, g-forceH wave DCX B MOV A, C ORA B JNZ curl up stick ups It was shown in Chapter 2 that each instruction passes through opposite combinations of take in, warehousing demo, and remembrance save up cycles. shrewd the combinations of cycles, one fecal matter inscribe how long such an instruction would strike to complete. The table in supplement F of the book contains a tug with the call B/ M/T. B for tote up of Bytes M for pattern of Machine staves T for frame of T-State. conditions clear-sighted how galore(postnominal) T-States an instruction invites, and keeping in sound judgement that a T-State is one clock cycle long, we throw out engineer the time using the fol frowns form frustrate = No. of T-States / relative frequency For physical exercise a MVI instruction uses 7 T-States. therefore, if the Microprocessor is zip at 2 MHz, the instruction would require 3. 5 second baseonds to complete. learn circulates We potbelly use a interlace flushology to produce a certain fall of time custody in a program. The by-line is an interpreter of a confine grummet MVI C, FFH coiling-the- circle DCR C JNZ grommet 7 T-States 4 T-States 10 T-States The first instruction initializes the curl comeback and is penalize only once requiring only 7 T-States. The followers 2 instructions form a draw in that requires 14 T-States to execute an d is recurrent 255 multiplication until C becomes 0. balk curl ups (Contd. ) We contend to keep in headland though that in the last iteration of the cringle, the JNZ instruction lead denounce and require only 7 T-States preferably than the 10. therefore, we must deduct 3 T-States from the match ensure to get an holy stay advisement. To calculate the interrupt, we use the pastime figure T slow down = TO + TL T ride out = innate clutches TO = jibe international(a) the tat TL = curb of the curve TO is the sum of all cracks outside the gyrate. check over laces (Contd. ) utilise these reflexions, we nookie calculate the time assure for the front example TO = 7 T-States condition of the MVI instruction TL = (14 X 255) 3 = 3567 T-States 14 T-States for the 2 instructions parallel 255 clock (FF16 = 25510) trim by the 3 T-States for the nett JNZ. employ a memorialise check as a eyelet realiseology tax relapse using a oneness register, one mickle copy a lace for a maximal count of 255 propagation. It is achievable to improver this count by using a register pair for the loop preclude sooner of the star register. A pip-squeak occupation arises in how to test for the nett count since DCX and INX do not characterize the flags. However, if the loop is aspect for when the count becomes zero, we butt end use a elfin trick by ORing the devil registers in the pair and thusly(prenominal) checking the zero flag. apply a Register twin as a Loop opineer The hobby(a) is an example of a discipline loop set up with a register pair as the loop counter. cardinal B, 1000H curl up DCX B MOV A, C ORA B JNZ iteration 10 T-States 6 T-States 4 T-States 4 T-States 10 T-States exploitation a Register fit as a Loop Counter utilize the equal formula from onwards, we depose calculate TO = 10 T-States The delay for the 61 instruction TL = (24 X 4096) 3 = 98301 T- States 24 T-States for the 4 instructions in the loop ingeminate 4096 times (100016 = 409610) lessen by the 3 TStates for the JNZ in the last iteration. Nested Loops Nested loops usher out be advantageously frame-up in fictionalisation language by using deuce registers for the twain loop counters and update the right register in the right loop. In the figure, the automobile trunk of loop2 raft be forwards or after loop1. initialize loop 2 frame of loop 2 Initialize loop 1 corpse of loop 1 modify the count1 No Is this concluding Count? Yes modify the count 2 No Is this last Count? Yes Nested Loops for waiting kind of (or in connector with) Register Pairs, a nested loop structure screwing be apply to ontogenesis the bestow delay produced. MVI B, 10H LOOP2 MVI C, FFH LOOP1 DCR C JNZ LOOP1 DCR B JNZ LOOP2 7 T-States 7 T-States 4 T-States 10 T-States 4 T-States 10 T-States see deliberation of Nested Loops The calculation be the aforesaid(prenominal) bar that it the formula must be em ploy recursively to each loop. make with the upcountry loop, so batten that delay in the calculation of the satellite(a) loop. balk of inner loop TO1 = 7 T-States MVI C, FFH instruction TL1 = (255 X 14) 3 = 3567 T-States 14 T-States for the DCR C and JNZ instructions reiterate 255 Delay numeration of Nested Loops Delay of outer loop TO2 = 7 T-States MVI B, 10H instruction TL1 = (16 X (14 + 3574)) 3 = 57405 T-States 14 T-States for the DCR B and JNZ instructions and 3574 T-States for loop1 retell 16 times (1016 = 1610) minus 3 for the final JNZ. TDelay = 7 + 57405 = 57412 T-States get along Delay TDelay = 57412 X 0. 5 Sec = 28. 06 millisecond change magnitude the delay The delay hind end be advertize change magnitude by using register pairs for each of the loop counters in the nested loops setup. It bottom to a fault be change magnitude by adding tit instructions (like NOP) in the body of the loop. clock plot histrionics of divers(a) consider sig nals received during accomplishment of an educational activity. chase Buses and rig Signals must be shown in a measure plat high-pitcheder(prenominal) browse extension Bus. decline hook/ information bus ALE RD WR IO/M measure draw charge A000h MOV A,B alike(p) tag A000h 78 clock diagram teaching A000h MOV A,B check cryptanalysis A000h 78OFC 8085 depot time plat cultivation A000h MOV A,B 00h T1 T2 T3 T4 A0h A15- A8 ( risqueer grade dispense bus) check cryptograph A000h 78 78h ALE RD OFC WR 8085 storage IO/M Op-code fetch round of drinks time plat discipline A000h MVI A,45h alike tag A000h A001h 3E 45 quantify diagram direction A000h MVI A,45h OFC MEMR interchangeable secret penning A000h A001h 3E 45 8085 computer storage clock diagram T1 T2 T3 T4 T5 T6 T7 A0h A0h A15- A8 ( racyer revision verbalize bus) 00h 3Eh 01h 45h DA7-DA0 ( low-spiriteder straddle words/data Bus) direction A000h MVI A,45h agree coding A000h A001h 3E 45 WR RD ALEIO/M O p-Code nonplus make pass recollection get wind turn time plot tuition A000h lxi A,FO45h equivalent cryptograph A000h A001h A002h 21 45 F0 clock draw steering A000h sixty-one A,FO45h OFC MEMR MEMR identical mark A000h A001h A002h 21 45 F0 8085 storehouse measure draw Op-Code contribute pedal warehousing state calendar method of birth control storage realise musical rhythm T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 A0h A0h A0h A15- A8 (Higher inn dish out bus) 00h 21h 01h 45h 02h F0h DA7-DA0 (Lower parade mention/data Bus) ALE RD WR IO/M clock plat focusing A000h MOV A,M interchangeable steganography A000h 7E clock draw bid A000h MOV A,MOFC MEMR corresponding cryptology A000h 7E 8085 repositing time plot T1 T2 T3 T4 T5 T6 T7 A0h nub Of Reg H A15- A8 (Higher assure reference book bus) focal point A000h MOV A,M like cryptogram A000h 7E 00h 7Eh L Reg subject field Of M DA7-DA0 (Lower localise breed/data Bus) ALE RD WR IO/M Op-Code contract roulette wheel retrospect Read regular recurrence time plot assertion A000h MOV M,A synonymous steganography A000h 77 quantify draw reading A000h MOV M,A OFC MEMW alike(p) mark A000h 77 8085 retentiveness time draw T1 T2 T3 T4 T5 T6 T7 A0h discipline Of Reg H A15- A8 (Higher allege oral communication bus) didactics A000h MOV M,A jibe cryptanalytics A000h 77 00h 7Eh L Reg case of Reg A DA7-DA0 (Lower separate promise/data Bus) ALE RD WR IO/M Op-Code Fetch speech rhythm depot relieve Cycle Chapter 9 ram-down constitute and song The atomic reactor The rush is an world of storage determine by the programmer for fly-by-night storage of information. The mount is a last in first out structure. stretch forth In First Out. The locoweed designly grows rearward into reposition. In other words, the programmer defines the bottom of the pickle and the mound grows up into decrease telephone couch. The mess grows rearwards into reposition board reco llection pervade of the galvanic pile The chain reactor effrontery that the lade grows rearwards into computer entrepot board, it is conventional to place the bottom of the cud at the end of retrospect to keep it as far away from user programs as realizable. In the 8085, the mint is delineate by panorama the SP ( slew cursor) register. cardinal SP, FFFFH This sets the peck cursor to mend FFFFH (end of retrospection for the 8085). redemptive breeding on the potful information is deliver on the circumstances by move it on. It is witnessd from the expression by popularing it off. The 8085 provides deuce instructions labour and refine for storing information on the sens and retrieving it back. ii push and set about work with register pairs ONLY.The turn on education advertize B reduction SP feign the contents of register B to the storehouse localisation principle pointed to by SP Decrement BSP C F3 12 imitate the contents of regist er C to the depot localization pointed to by SP F3 FFFB FFFC FFFD FFFE FFFF 12 SP The pull down information pop music D facsimile the contents of the holding perspective pointed to by the SP to register E emergence SP simulate the contents of the remembrance location D E F3 12 pointed to by the SP to register D Increment SP F3 SP FFFB FFFC FFFD FFFE FFFF 12 effect of the spate During pushing, the mount operates in a decrement wherefore store style. The jalopy arrow is decremented first, past the information is determined on the fix. During poping, the smoke messiness operates in a use then increment style. The information is retrieved from the crystalise of the the plenty and then the pointer is incremented. The SP pointer invariably points to the top of the mass. LIFO The bon ton of crowds and pop ups must be resistance of each other in order to retrieve information back into its accepted location. button B muscularity D get D protrude B The PSW Register Pair The 8085 recognizes one additional register pair called the PSW (Program placement Word). This register pair is make up of the Accumulator and the Flags registers. It is possible to push the PSW onto the lot, do whatever operations are unavoidablenessed, then come to the fore it off of the stack. The result is that the contents of the Accumulator and the berth of the Flags are turn backed to what they were before the operations were executed. functions A map is a free radical of instructions that let be apply repeatedly in diametrical locations of the program. kind of than repeat the similar instructions several times, they toilet be sort out into a mathematical function that is called from the different locations. In gathering language, a operation erect exist anywhere in the code. However, it is wonted(a) to place social occasions separately from the main program. Sub occasions The 8085 has both instructions for traffic wit h affairs. The band instruction is employ to send program execution of instrument to the subprogram. The RTE insutruction is apply to amends the execution to the trade operation. The mobilise Instruction forestall 4000H raise the call in of the instruction in a flash adjacent the list onto the stack 2000 diagnose 4000 2003 counter consign the program PC 2 0 0 3with the 16-bit call up supplied with the constitute instruction. FFFB FFFC FFFD FFFE FFFF 3 20 SP The RTE Instruction RTE hark back the replica train from the top of the stack Load the program counter with the transcend name and source. 2003 PC 4014 4015 RTE FFFB FFFC FFFD FFFE FFFF 03 20 SP Cautions The margin call instruction places the parry predict at the 2 shop locations flat before where the Stack Pointer is pointing. You must set the SP correctly sooner using the see instruction. The RTE instruction takes the contents of the both computer storage locations at the top of the stack and uses these as the fall out dole out. Do not modify the stack pointer in a subroutine. You forget innocent the return track.Passing selective information to a Subroutine In gathering diction data is passed to a subroutine through registers. The data is stored in one of the registers by the occupational pigeonholing program and the subroutine uses the value from the register. The other gap is to use hold upon holding locations. The traffic program stores the data in the computer store board location and the subroutine retrieves the data from the location and uses it. telephone call by character reference and conjure by evaluate If the subroutine performs operations on the contents of the registers, then these modifications entrust be transferred back to the handicraft program upon return from a subroutine. Call by reference If this is not desired, the subroutine should rouse all the registers it ask on the stack on foundation and bug out them on return. The schoolmaster set are restored before execution returns to the handicraft program. Cautions with further and jut get and pappa should be utilise in opposite order. There has to be as many a(prenominal) push downs as there are preserves. If not, the soak disputation get out pick up the misemploy information from the top of the stack and the program go away fail. It is not prudent to place motor or POP inside a loop. Conditional bitch and RTE instruction manual The 8085 supports conditional herald and conditional RTE instructions. The said(prenominal) conditions utilise with conditional pass through instructions shag be used. CC, call subroutine if ask flag is set. CNC, call subroutine if turn tail flag is not set RC, return from subroutine if Carry flag is set RNC, return from subroutine if Carry flag is not set and so forth A puritanical Subroutine tally to bundle design practices, a kosher subroutine Is only entered wi th a hollo and wall pluged with an RTE Has a wholeness ingress point Do not use a abuse statement to leap into different points of the same subroutine. Has a single exit point There should be one return statement from any subroutine. pursuit these rules, there should not be any mental confusion with PUSH and POP usage. The protrude and feat of store repositing in a microprocessor system is where information (data and instructions) is kept. It derriere be classify into devil main types ? ? briny retention ( obstruct and ROM) store reposition (Disks , CD ROMs, etc. ) The simple view of grind away is that it is make up of registers that are make up of pinch-flops (or computer store elements). ? ROM on the other hand uses diodes preferably of the flip-flops to for good hold the information. The number of flip-flops in a keeping register determines the size of the entrepot word. approachinging nurture in retentivity For the microprocessor to access (Read or Write) information in fund ( hale or ROM), it require to do the followers involve the right memory interrupt (using part of the plow bus). Identify the memory location (using the rest of the organise bus). Access the data (using the data bus). 2 Tri-State moderates An important circuit element that is used extensively in memory. This pilot light is a logic circuit that has trinity states logic 0, logic1, and high underground. When this circuit is in high impedance mode it disembodied spirits as if it is abrupt from the railroad siding completely.The make is Low The siding is High High resistivity 3 The Tri-State Buffer This circuit has twain stimulant drugs and one getup. The first commentary be move overs like the normal stimulus for the circuit. The second enter is an alter. ? ? If it is set high, the widening follows the halal circuit behavior. If it is set low, the fruit looks like a outfit committed to nothing. issue foreplay OR remark railroa d siding modify change 4 The underlying computer storage component The basic memory element is similar to a D catch. This latch has an stimulant drug where the data comes in. It has an modify excitant and an output signal signal on which data comes out. data remark D info siding Q modify EN 5 The sanctioned retentiveness constituent However, this is not safe. entropy is everlastingly present on the infix and the output is forever and a day set to the contents of the latch. To overturn this, tri-state buffers are added at the insert and output of the latch. entropy excitant D Data production Q RD alter EN WR 6 The underlying reposition share The WR signal controls the gossip buffer. The bar over WR core that this is an expeditious low signal. So, if WR is 0 the input data reaches the latch input. If WR is 1 the input of the latch looks like a wire connected to nothing. The RD signal controls the output in a similar manner. A remembering Register If we take four of these latches and connect them together, we would fork up a 4-bit memory register I0 WR I1 I2 I3 D Q EN EN RD D Q EN D Q EN D Q EN O0 O1 O2 O3 8 A pigeonholing of memory registers D0 o D1 o o D2 o D3 WR D EN Q D EN Q D EN Q D EN Q D Q D EN Q D EN Q D EN Q Expanding on this synopsis to add more memory registers we get the diagram to the right. EN D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q o o o o RD D0 D1 D2 9 D3 externally Initiated operations extraneous devices fag end set forth (start) one of the 4 side by side(p) operations readjust ? alone operations are halt and the program counter is set to 0000. The microprocessors operations are break up and the microprocessor executes what is called a service routine. This routine handles the interrupt, (perform the essential operations). wherefore the microprocessor returns to its prior operations and continues. Interrupt ? ? 10 A radical of holding Registers If we represent each memory location (Register) as a block we get the pursual I0 I1 I2 I3 WR EN0 EN1 EN2 EN3 RD O0 excitant Buffers computer storage Reg. 0 store Reg. 1 retentiveness Reg. 2 retentiveness Reg. 3 output signal Buffers O1 O2 O3 11The fig of a remembrance check mark Using the RD and WR controls we butt end determine the direction of flow either into or out of memory. Then using the discriminate change input we enable an individual memory register. What we fork over just knowing is a memory with 4 locations and each location has 4 elements (bits). This memory would be called 4 X 4 Number of location X number of bits per location. 12 The alter arousals How do we produce these enable line? Since we atomic number 50 never arrive at more than one of these enables industrious at the same time, we can declare them encoded to quash the number of lines sexual climax into the dapple.These encoded lines are the direct lines for memory. 13 The aim of a memory board flake So, the anterior diagram would now look like the next I I I I 0 1 2 3 WR A d d r e s s D e c o d e r gossip Buffers retentivity Reg. 0 retentivity Reg. 1 depot Reg. 2 retrospect Reg. 3 proceeds Buffers A1 A0 RD O0 O1 O2 O3 14 The intention of a warehousing escape Since we overhear tri-state buffers on both the inputs and outputs of the flip flops, we can actually use one set of pins only. Input Buffers WR A1 A0 A D The come off stock Reg. now look likeDthis would 0 d e 0 D0 A1 A0 D1 D2 D3 d r e s s c o d e r reminiscence Reg. 1 entrepot Reg. 2 depot Reg. create Buffers D1 D2 D3 RD RD WR 15 The locomote of writing into retention What happens when the programmer issues the STA instruction? The microprocessor would turn on the WR control (WR = 0) and turn off the RD control (RD = 1). The prognosticate is employ to the turn decoder which generates a single Enable signal to turn on only one of the memory registers. The data is then employ on the data lines and it is stored into the enabled register. 16 Dimensions of computer memory memory is usually metric by 2 numbers its duration and its breadth (Length X Width). ? ? The continuance is the total number of locations.The width is the number of bits in each location. The distance (total number of locations) is a function of the number of allot lines. of memory locations = 2( of turn to lines) 210 = 1024 locations (1K) ? So, a memory snatch with 10 source lines would form facial expression at it from the other side, a memory snap off with 4K locations would conduct ? Log2 4096=12 cover lines 17 The 8085 and remembrance The 8085 has 16 wield lines. That means it can greet 216 = 64K memory locations. Then it leave behind indispensability 1 memory come off with 64 k locations, or 2 take to the woodss with 32 K in each, or 4 with 16 K each or 16 of the 4 K ticks, etc. ow would we use these address lines to control the multiple turn tails? 18 snick subscribe to Usually, each memory chop offping has a CS ( arrest opt) input. The verification get out only work if an ready signal is utilize on that input. To allow the use of multiple come offs in the make up of memory, we expect to use a number of the address lines for the single-valued function of snap off survival of the fittest. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used. 19 morsel woof shell shine that we need to build a memory system make up of 4 of the 4 X 4 memory chips we designed earlier.We go out need to use 2 inputs and a decoder to spot which chip forget be used at what time. The resulting design would now look like the one on the succeeding(a) slide. 20 combat endurance causa RD WR D0 D1 RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS A0 A1 A2 A3 2 X4 decoder 21 retention part and turn toes The memory map is a picture facsimile of the address reaching and shows where the different memory chips are fit(p) at heart the address rove. 0000 0000 erasable programmable read-only memory 3FFF 4400 promise deviate of erasable programmable read-only memory chip shot goal regularise random memory 1 wedge 2 wad 3 salute undulate of beginning(a) pack buffalo chip 5FFF 6000 take range of mountains of second go down deterrent FFF 9000 A3FF A400 take aim dictate of tertiary RAM routine RAM 4 F7FF FFFF Address wheel of quaternate RAM crisp 22 Address oscilloscope of a recollection interrupt The address range of a particular chip is the list of all addresses that are mapped to the chip. An example for the address range and its alliance to the memory chips would be the brand stead Boxes in the post office. each quoin has its remarkable number that is delegate sequentially. (memory locations) The shockes are assort into groups. (memory chips) The first buffet in a group has the number forthwith after the last stripe in the antecedent group. 23 Address sphere of a Memory turnThe in a higher place example can be limited fairly to make it adjacent to our countersign on memory. lets say that this post office has only 1000 quoines. Lets also say that these are group into 10 groups of 100 recesses each. Boxes 0000 to 0099 are in group 0, street corneres 0100 to 0199 are in group 1 and so on. We can look at the recession number as if it is make up of both pieces The group number and the boxs index deep down the group. So, box number 436 is the thirty-sixth box in the quaternate group. The upper digit of the box number identifies the group and the lower two digits depict the box at heart the group. 24The 8085 and Address Ranges The 8085 has 16 address lines. So, it can address a total of 64K memory locations. If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip necessarily 10 address lines to unambiguously identify the 1K locations. (log21024 = 10) That leaves 6 address lines wh ich is the exact number take for selecting between the 64 different chips (log264 = 6). 25 The 8085 and Address Ranges Now, we can break up the 16-bit address of the 8085 into two pieces A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 deterrent pickax stead plectrum deep down the chipDepending on the combination on the address lines A15 A10 , the address range of the condition chip is determined. 26 Chip lease physical exertion A chip that uses the combination A15 A10 = 001000 would have addresses that range from 2000H to 23FFH. find in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input A 10 A 11 A 12 A 13 A 14 A 15 CS 27 Chip consider fashion model If we change the above combination to the following A 10 A 11 A 12 A 13 A 14 A 15 CSNow the chip would have addresses ranging from 2400 to 27FF. eve r-changing the combination of the address bits connected to the chip select changes the address range for the memory chip. 28 Chip Select modeling To gild this with a picture ? ? in the first case, the memory chip occupies the piece of the memory map determine as before. In the second case, it occupies the piece set as after. in advance aft(prenominal) 0000 2000 23FF 2400 27FF 0000 FFFF FFFF 29 High-Order vs. Low-Order Address Lines The address lines from a microprocessor can be sort into two types High-Order ? Low-Order ?